New Conference Paper Published

A new conference paper co-authored by Enrico Fraccaroli has been published in the proceedings of the 2024 IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS).

• Enrico Fraccaroli

We are excited to announce that our latest conference paper, titled “Assessing Robustness of Smart Systems via Multi-domain Analog Fault Simulation”, has been published in the proceedings of the 2024 IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS).

Abstract

Smart systems contain digital and analog components of several physical domains, e.g., electrical and mechanical. During the design phase, the fault injection, which checks the system functionality following the guidelines of ISO standard 26262, enhances the system’s robustness. Unfortunately, fault injection and simulation on the analog side are i) not fully standardized compared to their digital counterparts, ii) highly domain-dependent, and iii) performed separately from the digital. This article proposes to improve the design of smart systems by generating faulty scenarios through analog fault injection across several physical domains. By exploiting these faulty scenarios it is possible to improve the robustness of the analog part and simultaneously improve the quality of the digital part that controls the system functionality.

Details

  • Title: Assessing Robustness of Smart Systems via Multi-domain Analog Fault Simulation
  • Authors: Francesco Tosoni, Nicola Dall’Ora, Enrico Fraccaroli, Sara Vinco, Franco Fummi
  • Conference: IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS)
  • Year: 2024
  • Pages: 1-3
  • Keywords: ISO Standards, Control systems, Robustness, System analysis and design, Testing, Guidelines, Fault simulation, Design robustness

This paper highlights an innovative approach to improving the design and robustness of smart systems by employing multi-domain analog fault simulation. The proposed methodology enhances system functionality by generating and utilizing faulty scenarios, improving the analog and digital components simultaneously.

We thank our collaborators and colleagues for their invaluable contributions to this work. For more details, explore the links provided above.

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