New Conference Paper Published

A new conference paper co-authored by Enrico Fraccaroli has been published in the proceedings of the 2024 IEEE Latin American Test Symposium (LATS).

• Enrico Fraccaroli

We are excited to share that our latest conference paper, titled “Analog Fault Simulation: Trends and Perspectives in Analog Hardware Description Languages”, has been published in the proceedings of the 2024 IEEE Latin American Test Symposium (LATS).

Abstract

Analog Hardware Description Languages (AHDLs) provide a valuable alternative to existing proprietary means of implementing defect models and generic templates. Analog defect modeling in SPICE engines and in event-driven digital simulators is discussed, with a review of the state-of-the-art, an analysis of possibilities, and proposals for future enhancements of tools and standards to meet the challenges of achieving good coverage estimations at the system level. Moreover, we discuss the possibilities of using the EDACurry open-source framework to instrument transistor-level analog circuits to support defects templates written through AHDL, e.g., Verilog-A.

Details

  • Title: Analog Fault Simulation: Trends and Perspectives in Analog Hardware Description Languages
  • Authors: Nicola Dall’Ora, Enrico Fraccaroli, Renaud Gillon, Franco Fummi
  • Conference: IEEE 25th Latin American Test Symposium (LATS)
  • Year: 2024
  • Pages: 1-2
  • Keywords: Reviews, Instruments, Integrated circuit interconnections, Analog circuits, SPICE, Market research, Circuit faults, Analog Circuits, Fault Simulation, Defect Model Templates, AHDLs

This paper discusses the role of Analog Hardware Description Languages (AHDLs) as an alternative to proprietary implementations for analog defect modeling and fault simulation. The study reviews the state-of-the-art in SPICE-based and event-driven simulators, analyzes current challenges, and proposes enhancements for achieving better system-level coverage estimations. It also highlights the use of the open-source EDACurry framework to instrument transistor-level circuits using AHDLs such as Verilog-A.

We thank our collaborators for their efforts in advancing this research. For more details, explore the links provided above.

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